Meta-stability of logic circuits capable of storing a logic state, such as a latch, a multi-stage latch, or a flip-flop, has been a known problem in logic designs for many years. Meta-stability is inherent in storage elements that incorporate feedback and, under certain conditions, may occur even in properly designed circuits. A storage element may enter a meta-stable state if the setup or hold timing parameters of the storage element are not met. In synchronous circuit designs, most logic paths can be established so that the setup and hold parameters are inherently designed to be met. But, for data values that are received from a clock domain that is asynchronous to the clock domain of receiving circuitry, there is a chance that an input line may switch at a time that renders the setup and hold time parameters unmet in the receiving storage element.
A common design technique to counter this problem is the use of synchronizing circuits on a line coming into a clock domain within a logic design, where the line is driven with data that is asynchronous or is driven from a different clock domain. A synchronizing circuit couples the input line to the input of a latch or flip-flop (hereinafter simply referred to as a storage element) which is then clocked using the clock of the clock domain that the input line is entering. Some synchronizing circuits may use additional cascaded storage elements, with the output of the first storage element driving the input of the second storage element and so on, all clocked by the same clock. Most synchronizing circuits use at least two cascaded storage elements, although some synchronizing circuits may use additional cascaded storage elements to increase mean time between failures (MTBF) at the cost of increased latency in detecting changes on the input line.
The idea behind a synchronizing circuit is not to eliminate meta-stability, as meta-stable states may still occur in the storage elements if the input line happens to switch during the setup/hold window. But, by using only the output of the first storage element to drive the second storage element, potentially disruptive effects of meta-stability may be avoided. This is because as long as the output of the first storage element has settled to a valid state in time to meet the setup time of the next storage element, the output of the second storage element will not go into a meta-stable state. Further, each additional cascaded stage reduces the probably of the final stage of the synchronizing circuit being in a meta-stable state.
The rate at which the output of a storage element settles to a valid logic level from a meta-stable state is related to an exponential time constant. This time constant is known in the industry as the regeneration time-constant or τ (Tau). While Tau is an intrinsic parameter of a particular circuit, it may also be affected by supply voltage and temperature, and typically increases with lower supply voltages and/or lower temperatures.
Tau is helpful in understanding the meta-stable state of a storage element, and may be used to calculate a MTBF. But other information about the design may also be necessary to determine a MTBF, which is often an important design goal. Information such as the clock period, clock duty cycle, rate of input data transitions, and the number of stages of a synchronizer may all impact the MTBF.
The ability to calculate MTBF can be important to understanding whether a design meets its design goals. In the past, Tau has often been estimated as being proportional to the propagation delay of an inverter circuit with a fan-out of four (FO4). FO4 is easily measured for any particular process technology, supply voltage, and temperature. But in modern semiconductors with geometries below 100 nanometers (nm), the relationship between Tau and FO4 may no longer be valid, leaving no easy way to calculate MTBF.